The reuse of pre-designed and pre-verified Intellectual Property (IP) blocks or cores has been identified heretofore as something that can enable very large systems-on-chip designs. However, the lack of appropriate tools and the increasing complexity of such cores makes them inherently difficult and error-prone to use. One of the main problems in using cores is the generation of all interconnections among them.
Of late, there have been profound, fundamental changes in the way very large scale integration (VLSI) systems are designed. The use of IP blocks or cores, in many different forms (hard, soft, firm) for SoC design is now being recognized as vital, if not an absolute necessity. Since these cores are pre-designed and pre-verified, a designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components.
However, the lack of appropriate tools for using and integrating these cores has hindered meaningful progress. In fact, SoCs have grown considerably in size in recent years. It is currently commonplace to find SoC designs with well over thirty cores, with the percentage of core content varying from 50% to almost 95%. In this connection, reference is made to A. Rincon, W. Lee and M. Slatery, “The Changing Landscape of System-on-a-Chip Design” (IBM MicroNews, 3rd Quarter 1999, Vol. 5, No. 3, IBM Microelectronics) and A. Rincon, C. Cherichetti, J. Monzel, D. Stauffer and M. Trick, “Core Design and System-on-a-Chip Integration” (IEEE Design & Test of Computers, October/December 1997).
In order to understand the complexity of designing such systems, it is instructive to consider the complexity of the cores being used. Current cores can be extremely complex, with tens of thousands of gates and hundreds of pins. Designing using such cores has become a major problem because it requires designers to understand the functionality, interfaces and electrical characteristics of complex cores such as microprocessors, moving picture experts group (MPEG) decoders, direct memory access (DMA) controllers, etc. Moreover, the situation is further complicated by the fact that cores may be designed by different IP providers with different interface protocols, but need to be made interoperable with other cores.
An initial task in building an SoC is the integration of the cores into a top-level design, which can then be simulated and synthesized. This integration task, nowadays, is largely a manual and error-prone process because it requires the designer to understand the functionality of hundreds of pins in various cores and determine which pins should be connected together. This tedious manual process can lead to interconnection errors being introduced into the SoC which may not be detected until much later in the process. Problems such as these severely limit the advantages of using pre-designed IP blocks.
In view of the foregoing, a need has been recognized in connection with overcoming the shortcomings and disadvantages discussed above in connection with conventional arrangements.